{"id":18,"date":"2026-10-15T14:33:42","date_gmt":"2026-10-15T14:33:42","guid":{"rendered":"https:\/\/blog.amitdhiman.com\/?p=18"},"modified":"2026-10-15T14:33:42","modified_gmt":"2026-10-15T18:48:14","slug":"tech-risc-v-open-isa-first-program","status":"publish","type":"post","link":"https:\/\/blog.amitdhiman.com\/?p=18","title":{"rendered":"RISC-V for Software Developers: Learn the ISA Without Buying a Board"},"content":{"rendered":"

You do not need to design a processor to learn something useful from RISC-V. For embedded developers, systems programmers, and engineers evaluating hardware platforms, compiling a small program reveals the distinction between an instruction set, a software calling convention, and an actual chip. That distinction prevents expensive assumptions when choosing a development board or planning a port.<\/p>\n

What is open, exactly?<\/h2>\n

RISC-V is an instruction set architecture, or ISA: a specification of the instructions and architectural behavior software can rely on. It does not prescribe a particular cache, clock frequency, fabrication process, or board layout. Two processors implementing compatible instructions can have very different practical characteristics.<\/p>\n

RISC-V International<\/a> describes the ISA as an open, royalty-free standard that can underpin open or proprietary products. This does not mean every implementation publishes its hardware design, that a chip costs nothing, or that peripheral drivers are automatically available. Evaluate the actual implementation and its support commitments.<\/p>\n

The base architecture and many extensions are established. Additional specifications and platform ecosystems continue to develop. Avoid treating the whole architecture as either experimental or universally interchangeable. For software planning, a precise list of supported extensions and a maintained operating-system distribution is more useful than a broad compatibility label.<\/p>\n

Start with Linux user-space emulation<\/h2>\n

The shortest practical exercise uses a Linux development environment, a RISC-V cross-compiler, matching target C library files, and QEMU user-mode emulation. On Windows, a suitable WSL Linux distribution is one option. This exercise runs a Linux program, not bare-metal firmware, and does not emulate an entire board.<\/p>\n

On a Debian or Ubuntu release offering these packages, install gcc-riscv64-linux-gnu<\/code>, libc6-dev-riscv64-cross<\/code>, and qemu-user<\/code> through the distribution package manager. Confirm that riscv64-linux-gnu-gcc<\/code> and qemu-riscv64<\/code> are on your PATH. Package availability and names differ across distributions.<\/p>\n

Create a file named reading.c<\/code> with this deliberately small program:<\/p>\n

#include <stdio.h>\n\nint main(void) {\n    const int samples[] = {12, 15, 18, 11};\n    int total = 0;\n    for (unsigned i = 0; i < 4; ++i) {\n        total += samples[i];\n    }\n    printf(\"total=%d\\n\", total);\n    return 0;\n}<\/code><\/pre>\n
Compile for a common 64-bit Linux target and run the result:<\/p>\n
riscv64-linux-gnu-gcc -O2 -march=rv64gc -mabi=lp64d -static reading.c -o reading-rv64\nqemu-riscv64 .\/reading-rv64<\/code><\/pre>\n
The expected output is total=56<\/code>. Static linking avoids locating a separate target dynamic loader for this introductory example; it requires the target static libraries to be installed. If linking fails because those libraries are missing, fix the target toolchain installation. Do not substitute the host machine’s libraries.<\/p>\n
Read the options before generalizing the result<\/h3>\n
-march=rv64gc<\/code> selects the allowed instruction set. -mabi=lp64d<\/code> selects a calling convention, including how floating-point arguments are passed. The GCC RISC-V options reference<\/a> explains both. Your compiler, libraries, operating system, and processor must agree on the relevant choices.<\/p>\n
Next, generate assembly with riscv64-linux-gnu-gcc -O0 -march=rv64gc -mabi=lp64d -S reading.c -o reading.s<\/code>. Compare it with output built at -O2<\/code>. Constant input may allow the optimizer to remove much of the calculation. That is an opportunity to understand compilation, not evidence of processor performance.<\/p>\n
Use emulation for the right questions<\/h2>\n
Consider an industrial gateway that summarizes sensor readings. User-mode emulation can help check that its portable C code builds and produces expected results before hardware arrives. It does not validate the gateway’s serial interface, interrupt behavior, boot firmware, or power consumption.<\/p>\n
The QEMU user-space documentation<\/a> explains how guest system calls interact with the host environment. Emulation is not a dependable predictor of native throughput, and it is not automatically a security boundary for unknown executables. Use trusted test programs and appropriate isolation for untrusted inputs.<\/p>\n
Before choosing a board<\/h2>\n
    \n
  • Confirm the exact ISA extensions, ABI, memory capacity, and peripheral requirements of your application.<\/li>\n
  • Check maintained kernel support, boot documentation, debugger access, and recovery procedures.<\/li>\n
  • Identify binary-only dependencies and assembly written for another architecture before estimating porting effort.<\/li>\n
  • Budget for engineering time, test hardware, support, and long-term updates alongside the device itself.<\/li>\n<\/ul>\n
    An open ISA enables inspection and implementation choice, but it does not certify secure boot, physical attack resistance, or timely firmware updates. Those are platform-specific questions.<\/p>\n
    Record the target configuration in the build system instead of relying on a developer’s machine defaults. Keep a portable baseline build, and place optional optimized paths behind explicit capability checks where needed. This makes unsupported instructions easier to diagnose and prevents a successful test on one processor from becoming an accidental promise about every RISC-V device.<\/p>\n
    Your next step is to cross-compile one real dependency and run its correctness tests under emulation. Move to a representative board when you need answers about peripherals, timing, thermals, and deployment reliability.<\/p>\n","protected":false},"excerpt":{"rendered":"
    Cross-compile and emulate a small RISC-V program, understand ISA and ABI choices, and learn what open architecture does and does not guarantee.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[11],"tags":[],"class_list":["post-18","post","type-post","status-publish","format-standard","hentry","category-software-development"],"_links":{"self":[{"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=\/wp\/v2\/posts\/18","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=18"}],"version-history":[{"count":1,"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=\/wp\/v2\/posts\/18\/revisions"}],"predecessor-version":[{"id":32,"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=\/wp\/v2\/posts\/18\/revisions\/32"}],"wp:attachment":[{"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=18"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=18"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.amitdhiman.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=18"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}